The dominant semiconductor technology used for the manufacture of ultra-large scale integrated (ULSI) circuits is the metal-oxide-semiconductor field effect transistor (MOSFET) technology. A MOSFET consists of source and drain regions separated by a channel region. Current flow between the source and drain through the channel is controlled by a voltage applied to a gate electrode lying adjacent to the channel and separated from it by an oxide dielectric. Traditionally, the source, channel and drain were embedded in a silicon substrate. The oxide dielectric was formed on the upper surface of the channel region, and the gate electrode was deposited on top of the oxide. Efforts to scale MOSFETs into the sub-50-nanometer (nm) regime have led to the development of vertical, multiple-gate MOSFETs, some of which are known as FinFETs, in which a thin, fin-shaped active region is formed which rises vertically from a substrate, typically a silicon on insulator (SOI) substrate (also sometimes known as a semiconductor on insulator substrate). The fin contains the source, channel and drain of the transistor.
FIG. 1 illustrates in plan view a typical (albeit idealized) prior art fin-FET structure 2. The structure 2 includes a first transistor 4 and a second transistor 6 formed in an active layer mesa 31. Transistors 4 and 6 share a common source/drain region 8. Transistor 4 also has source/drain region 10 and transistor 6 has source/drain region 12. One skilled in the art will recognize that transistors 4 and 6 can be of either n-type or p-type, respectively, and form a common CMOS transistor pair. Each transistor 4 and 6 has a channel region, not shown, which underlies gate electrodes 14 and 16, respectively. Also shown is similarly configured CMOS transistor pair 18 and 20 formed in active layer mesa 32 and sharing a common source/drain region 22. Transistor 18 also has source/drain region 24 and transistor 20 has source/drain region 26. Note that transistors 4 and 18 share a common gate electrode 14 and that transistors 6 and 20 share a common gate electrode 16.
The gate electrodes 14, 16 are formed over a gate dielectric, as is well known in the art. After formation of the gate dielectric layer (not shown), a polysilicon layer is typically blanket deposited over the entire structure and subsequently etched to form gate electrodes 14 and 16. FIG. 2a shows a cross sectional view of the structure along the cross section line shown as a-a in FIG. 1. As such, FIG. 2a illustrates details regarding transistors 4 and 18. Transistors 6 and 20 would have a similar cross section. As shown, mesas 31, 32 (in which transistors 4, 6 and 18, 20 are formed, respectively) have rectangular cross-sections and vertical sidewalls. A dielectric layer has been formed over the entire structure and patterned to form gate dielectric 28 for transistor 4 and gate dielectric 30 for transistor 6 (gate dielectrics for transistors 6 and 20 would be formed simultaneously). A polysilicon layer has been blanket deposited over the entire structure and has been patterned to form gate electrode 14 over transistors 4 and 18.
FIG. 2b illustrates the cross sectional view of the structure along the cross section line shown as b-b in FIG. 1. This view shows cross-sections of mesas 31 and 32 wherein are formed common source/drain regions 8 and 22, respectively, after the polysilicon layer has been patterned to form gate electrodes 14 and 16. Note that it is undesirable to have polysilicon remaining over the common source/drain regions (or over any regions that are not overlying the channel regions). Because of the vertical sidewalls of mesas 31 and 32, however, it is quite difficult to completely remove all of the polysilicon layer during the etching process. Polysilicon residual regions 34 often result from incomplete etching of the polysilicon layer from the mesa sidewalls, as is shown in FIG. 2b. One approach to overcoming the polysilicon residual regions is to over-etch the polysilicon layer. This over-etching, however, can damage the mesa region in which the source/drain regions will be formed, or may damage the underlying gate dielectric.
After the gate electrode has been etched, the source/drain regions are formed, typically by ion implantation, as is well known in the art. It is difficult to uniformly dope the sidewall portions of the source/drain regions without using an oblique implantation angle. However, when mesas (e.g., mesas 31 and 32) are closely spaced together, shadowing occurs wherein one mesa will cast a “shadow” on an adjacent mesa, thus preventing some of the desired ion implantation from occurring. Additionally, when mesas are formed orthogonally to one another, an oblique implantation angle could result in dopants being driven into the channel region, thus degrading device performance.
Another shortcoming of prior art structures is shown in FIG. 3. As shown, an inter-layer dielectric layer (ILD) is typically formed over the gate electrodes. This ILD layer is typically formed by e.g., LPCVD, PECVD, HDP, APCVD, or the like. The material typically comprises TEOS, BPTEOS, BPSG, PSG, SACVD, O3 TEOS, PEOX, or combinations thereof. In some embodiments, the ILD could includes an Si3N4 or SiON contact etch stop layer (under layer) and/or an anti-reflective coating (ARC)/hard mask layer (top layer). FIG. 3 shows this coating 41 after it has been polished to produce a planar upper surface. The ILD coating provides a substrate on which to fabricate another layer of circuit elements. If the region to be filled between fins has a high aspect ratio (the ratio of the height of the fins to the distance between them), then voids can form during the process of depositing the ILD coating. Such a void is shown in FIG. 4 at 42. Additional processing steps are often employed to prevent the formation of such voids. For example, a partial ILD coating can be deposited and then etched to form trenches between fins with sloped walls. Then, a final coating is deposited that fills the trenches without forming voids. This dual-step approach causes additional process steps that add to the cost and decrease overall yield, however.
What is needed, therefore, is a mesa structure that allows for improved gate electrode formation, source/drain implantation, and ILD deposition.